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IN PH-491 : SYLLABUS & STUDY NODE ARE NOTE MATCHING ... PLEASE GIVE ME A REPLY RELATED TI THIS..
I forgot to mention vdd in dff using transmission gate(vlsi).can all Marks be deducted??it was a 10 mark question K4
Is short note on fpga architecture and lut fpga architecture same as short note on fpga (vlsi)?
I am a final year b.tech student;appearing for gate in 2019.but my 7th semester vlsi exam went not well. Can't I get admission for m.tech if I get supply?because supplymentary exam will be held on September. And I don't know when the admission will start for m.tech in iit/others??
If I draw diagram instead of definition as per the requirement in a 5 markquestion;can I get Marks??