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Rajni

An SRAM is designed to fill two needs: to provide a direct interface with the CPU at speeds not attainable by DRAMs and to replace DRAMs in systems that require very low power consumption. In the first role, the SRAM serves as cache memory, interfacing between DRAMs and the CPU. The interface uses a multiplexed address and data bus to reduce the number of port pins required. The lower address bits are held in a latch while data is transferred. Fig 7 shows the block diagram of the hardware connection between the 8051 microcontroller and the SRAM. The multiplexed address/data bus 'AD[7..0]' support the lower 8 bits of the address and the 8 bits of data. This configuration allows the lower address lines to be held by the latch while the SRAM and 8051 transfer data, such that 8 additional ports for data transfer are not necessary. The 'A[15..8]' supply the upper 8 bits of the address. 'A16' acts as a bank select between the two 64 Kbyte banks. A '0' is bank one and '1' is bank two. 'RD' is the read strobe (operates active low). 'WR' is the write strobe (operates active low). 'ALE' is the address latch signal that holds the lower 8 address bits during data transfer. 'CS' is the SRAM chip select (operates active low).