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Rajni

A low power 16-bit ALU has been designed, fabricated and tested at the transistor level. The designed ALU performs 16 instructions and has a two-stage pipelined architecture. For low power consumption, we propose a new ALU architecture which has an efficient ELM adder of propagation (P) and generation (G) block scheme. The operation of an adder of the proposed ALU is disabled while the logical operation is performed and vice versa, and outputs of P block are separated to become dual bus to reduce switching capacitances during the ALU operation. Double edge-triggered flip-flops are used to reduce the switching activity for the register. The proposed ALU was fabricated with 0.6 μm single-poly triple-metal CMOS process. As a result of chip test, addition time is about 10 ns for the proposed ALU with 3.3 V supply voltage and the average power consumption is 33 mW at 50 MHz